Address logging errors can occur in the following situations: recommends that all transactions on the HPS-to-FPGA and lightweight HPS-to-FPGA bridges be completed before shutting down and resetting the bridges.If the system is unable to meet this recommendation, the Arria 10 So C device has a built-in timeout that can be enabled to force all outstanding transactions on the bridge to complete.

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The Arria 10 So C device supports both a default and a faster boot clock mode.

The majority of multi-processing code examples follow styles that do not expose this erratum.

Therefore, this erratum occurs rarely and is likely to affect only very specific areas of code that rely on a read-ordering behavior.

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To use faster boot clock frequencies, you can change the CSEL fuses from their default setting of 0x0 to any value between 0x7 to 0x E.